Performance Issues in Ring-Based Multiprocessor Systems

Sung Woo Chung is the designated presenter and he will attend the conference should his paper accepted Primary technical subject area : A. Computer Architecture and Super Computing 1. Introduction As microprocessors speeds continue to improve at a very fast rate the bandwidth requirements for system level interconnections in multiprocessor systems rule out the use of shared buses even for small-scale multiprocessor system. Buses are still popular for connection within a cluster. However, unidirectional point-to-point links replaces buses as the interconnection fabric for recent multiprocessor systems, because they increase the total network bandwidth of systems by pipelining effect and they operate at a very high speed. Sequent Computer Systems introduced ring-based system, STiNG[1], which supported one-way transmission on the ring. They used the Scalable Coherent Interface(SCI) specification[2]. Luiz A. Barroso and Michel Dubois suggested slotted ring–based multiprocessor system called Express Ring[3]. The PANDA[4] was presented to enhance the performance by reducing the data miss latency. To widen ring bandwidth, the Data General AviiON[5] architecture uses two SCI[2] rings operating at 500 MB/sec each to provide an aggregate bandwidth of 1 GB/sec to the system. Each SCI ring uses point-to-point links to achieve the high signal integrity necessary for high-frequency data transport. The rings(One is clockwise and the other is counterclockwise) and the packet routing are configured to circulate in opposite directions for increased performance by choosing the ring with the shortest path to the target cluster. Although researchers have shown the benefits of ring-based multiprocessor systems[3,4], there has not yet been a detailed or realistic analysis of effects of each component in ring-based multiprocessor systems. Such an analysis is required for system architects to select cost-effective components in ring-based multiprocessor systems.